1. Field of the Invention
The present invention relates to clock signal generation, and more particularly, to adjusting the phase of a frequency-locked clock.
2. Background of the Invention
The past several years have witnessed a dramatic increase in the capabilities of high-speed, high-density communications systems. Such systems may include, but are not limited to, broadband communication systems using cable modems, cellular communications systems, satellite communication systems, fiber to the home (FTTH) communications networks, and board-to-board interconnections in a myriad of electronic devices.
In many of these systems, a remote electronic device must replicate a signal provided by another electronic device. One of the more common reasons an electronic device replicates a signal provided by another device is to provide clock synchronization between two or more electronic devices. There are many reasons why remotely distributed devices may need to have their clocks synchronized. In particular, in a digital communication system the receiving device must be properly synched to a sending device to enable the efficient processing and interpretation of an incoming data stream. For example, in order for a data signal to be correctly reconstructed at the receiving end, the transmitted data must be regenerated with the fewest possible bit errors, requiring low noise and timing jitter (phase noise) at the clock generation source. In high speed data communication systems, precise clock signal generation is important to enhance efficiency and to reduce error rates that may be caused by jitter.
One type of communications system where clock signal regeneration is commonly used is a cable modem-based broadband communications system. Within a cable modem-based broadband communication system the two principle devices are cable modems and cable modem termination systems (CMTSs). In a broadband communications network that uses cable modems, typically many cable modems are connected to a CMTS. Cable modems are located at customer premises and typically connected to personal computers through an Ethernet connection. CMTSs are typically located within a service provider's network center, often known as a headend location. CMTSs exchange data with multiple cable modems at high speeds. Importantly, CMTSs transmit clock signals to cable modems for synchronization that is critical to ensuring efficient operation and high throughput.
Consumer demand for faster communication speeds and increased performance require communication system optimization. In the case of high speed cable modems, for example, the cable industry has recently released the DOCSIS 2.0 specification that introduced a new requirement that cable modem systems support synchronous code division multiple access (CDMA) communication schemes to achieve higher transmission rates. Furthermore, the DOCSIS 2.0 specification requires that ramp-down of one burst of data may completely overlap the ramp-up of the following burst of data, so that the transmitted data envelope is never zero. As a result the system timing for synchronous transmissions from various cable modems that are connected to a single CMTS must provide precise timing accuracy so that different cable modems do not appreciably interfere with each other. Synchronous transmission requires precise synchronization so that multiple cable modems can transmit simultaneously.
DOCSIS 2.0 recognizes that the timing of transmissions from a cable modem to a CMTS may need to be adjusted during operation. In particular, section 6.2.19.1 of DOCSIS 2.0 specifies that a CMTS must be able to provide a target phase offset, referred to as a ranging offset, to a cable modem. In the case of cable modems, the target phase offset is a delay correction applied by the cable modem to the CMTS upstream (from cable modem to CMTS) frame time of a clock signal derived at the cable modem. The target phase offset can represent an adjustment equal to roughly the round-trip delay of a signal between the cable modem and the CMTS, and is needed to synchronize upstream transmissions. The requirements specify that the cable modem should be able to implement the timing correction with an accuracy of plus or minus two nanoseconds to support synchronous CDMA operation.
FIG. 1 illustrates one type of clock signal regeneration system 100 that includes numerically controlled oscillator (NCO) 110 and clock source 120. Frequency control word (FCW) 130 and Clk_in signal 140 are input into NCO 110 to produce Clk_out signal 150. FCW 130 is supplied to NCO 110 to lock the frequency of Clk_out 150 to a particular external oscillation source. Typically, a timing recovery circuit provides FCW 130 based on a replicated frequency of an incoming clock signal from another device. Clock regeneration system 100 does not provide a means for dynamically adjusting the phase of the output signal.
What is needed is a cost-effective system and method for adjusting the phase of a frequency-locked clock.